This product is the optional add‑on companion board of the PCIed, PCIem, PCIe boards. This is recommended in those cases where a local CPU (e.g. NIOSII core) is required for improving system performances, such as interrupt response time or dedicated pre-processing.
To reduce the number of Fpga I/O pins required to allow the use of the FPGA boards J2, the SRAM board has been designed with a partial multiplexed Address/Data Interface.
The GEB MSRAM IP, a Multiplexed Static Ram Controller , fully compatible with QSYS is recommended to interface PCIE Sram module to PCIE cards family.