VEC100: Introduction to VHDL
This two-day course is a general introduction to the VHDL language and its use in programmable logic design. The emphasis is on the synthesis constructs of VHDL; however, you will also learn about the simulation constructs. You will gain a basic understanding of VHDL to enable you to begin creating your design file. In the hands-on laboratory sessions, you will put this knowledge to the test by writing simple but practical designs. You will also learn the basic instructions needed for operating both the synthesis and simulation tools of the Quartus® II software.