MS-Windows 64bits, Seven: Dual SGDMA Master/Slave System (PCIe Master/Target) Drivers, QSYS and Demo Sources
The system is targeted for extreme DMA Application. It includes a system with 2 SGDMA channels.
The two SGDMA channels are configured one in input and one in output. Customer’s logics can be connected to user Inputs/Outputs pins. The mux, under control of an Avalon’s register, can route the DMA channels ST interface from the I/O pins to TB module. The TB Pheripheral can be used to test the system and measure its performance. The TB peripheral contains a timer, a loopback, a speed programmable pattern checker and/or generator. The test mode of TB block can be programmed from Avalon bus. The fifos inside the input output data path allow to mantain the data transfer rate during DMA descriptor and TLB handling in large DMA. A simple test programm, using the TB block, tests and measures the performance in different driver layouts.