QUARTUSII Advanced Timing Analysis

QUARTUSII Advanced Timing Analysis
QUARTUSII Advanced Timing Analysis
Brand: Geb Enterprise
Product Code: VEC125
Availability: In Stock
Price: 960.00€
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VEC125: QUARTUSII Advanced Timing Analysis

Using the Quartus® II software  and building upon your basic understanding of creating Synopsys Design Constraint (SDC) timing constraints, this class will guide you towards understanding, in more depth, timing exceptions. You will learn how to apply timing constraints to more advanced interfaces such as source synchronous single-data rate (SDR), double-data rate (DDR) and LVDS, as well as clock and data feedback systems. You will discover how to write timing constraints directly into an SDC file rather than using the GUI and then enhance the constraint file using TCL constructs. You will also perform timing analysis through the use of TCL scripts.

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