VEC222: Training about Altera PCIe IP uses SPECIAL EDITION
Are you beginning or working on a design that uses one or more PCI Express®; interfaces? Do you have questions regarding bringing up your FPGA’s PCIe® link? Then this course should be of interest to you!
We'll start with a high-level overview of the PCI Express protocol and from there you'll learn the design flow to target the Hard IP for PCI Express blocks found in Cyclone® V, Arria® V and Stratix® V devices, particularly when using the Qsys system design tool.
You'll see how to debug and test your PCIe links, both through simulation and in-system. You'll discover advanced device features to add more flexibility and capability to your PCI Express-based design.
By the end of the training, you'll feel comfortable getting your own device’s PCIe link up and running.
The Special edition includes an intensive exercises program for 2-3 attendees. I will be tought on date choosen by customers at least 1 month before the class starts allowing to obtain license and hardware needed to perform the mentioned exercises program.